module Mrf2_ram_wrap
#(
   parameter                RAM_TYPE   = "REG"
  ,parameter                ADDR_WIDTH = 1
  ,parameter                DATA_WIDTH = 1
  ,parameter                DATA_DEPTH = 1
)
(
   input                    i_rclk
  ,input                    i_wclk
  ,input                    i_rd
  ,input                    i_wr
  ,input  [ADDR_WIDTH-1:0]  i_addr
  ,input  [DATA_WIDTH-1:0]  i_wdata
  ,output [DATA_WIDTH-1:0]  o_rdata
);

generate
  if(RAM_TYPE == "REG") begin

    reg  [DATA_WIDTH-1:0] ram_mem [DATA_DEPTH-1:0];
    reg  [DATA_WIDTH-1:0] ram_rdata               ;

    always@(posedge i_wclk) begin
      if(i_wr) begin
        ram_mem[i_addr] <= i_wdata;
      end
    end

    always@(posedge i_rclk) begin
      if(i_rd) begin
        ram_rdata <= ram_mem[i_addr];
      end
      else begin
        ram_rdata <= {DATA_WIDTH{1'bx}};
      end
    end

    assign o_rdata = ram_rdata;

  end
endgenerate

endmodule
